The present invention relates to the connection of spares between multiple programmable devices, and more particularly to the connection of spares between three or more such devices.
Complex signal processing, and other complex processing applications frequently employ multiple complex programmable logic devices on a single printed circuit board. While each of the complex logic devices frequently has one-hundred or more conductive pins to which electrical interconnections can be made, each of which can be programmatically designated for use as an input or an output, or both, the printed circuit board, itself, must be laid out in accordance with the particular functions to be carried out by the complex programmable logic devices.
For example, on a transmit/receive controller used in an Intelsat TDMA earth station, which is employed in large scale satellite communications, ten field programmable gate arrays may be employed in combination on a single printed circuit board in order to format signal bursts, perform forward error correction coding, perform digital signal processing necessary to detect, error correct and route bursts, and other digital transmit and receive functions. While the field programmable gate arrays can be programmed, and reprogrammed, in order to debug, or update their programming, the electrical interconnections provided on the printed circuit board on which the field programmable gate arrays are connected are fixed at the time the printed circuit board is made.
In order to accommodate additional electrical interconnections that may be needed as the programming in the field programmable gate arrays is updated, "spare" electrical interconnections have frequently heretofore been made between each of the field programmable gate arrays on the printed circuit board. Unfortunately, if just five additional interconnect wires are made between each of 10 field programmable gate arrays, this results in an additional 225 electrical interconnections that must be made on the printed circuit board. (In addition to the interconnections already needed to implement whatever functions are to be performed by the field programmable gate arrays). Furthermore, five additional electrical interconnections, problematically, may be too many additional interconnections between some of the field programmable gate arrays, (i.e., may be more than will ultimately be needed once the programming in the field programmable gate arrays is updated) and may be far too few additional interconnections between others of the field programmable gate arrays, (i.e., may be less than will ultimately be needed) depending on the changes in programming that are made in the future to the field programmable gate arrays. Nonetheless, the above approach requires the addition of 225 additional electrical interconnections, and therefore, poses a significant design burden on the printed circuit board designer.
The present invention advantageously addresses the above and other needs.